Many different kinds of Integrated circuits (IC's) are prone to damage and failure from an electro-static-discharge (ESD) pulse. ESD failures that occur in the factory contribute to lower yields. ESD failures may also occur in the field when an end-user touches a device.
Various ESD-protection structures have been placed near input, output, or bi-directional I/O pins of ICs. Many of these protection structures use passive components such as series resistors, diodes, and thick-oxide transistors. Other ESD structures use an active transistor to safely shunt ESD current.
As manufacturing ability improves and device sizes shrink, lower voltages are applied to transistors during normal operation. These smaller transistors are much more susceptible to over-voltage failure but can operate with a lower power-supply voltage, thus consuming less power and producing less heat.
Such smaller transistors are often placed in an internal “core” of an IC, while larger transistors with gate lengths that are above the minimum are placed around the core in the periphery. ESD-protection structures are placed in the periphery using these larger transistors.
Thinner gate oxides of the core transistors can be shorted, and substrate junctions melted, by relatively small capacitively-coupled currents applied to the tiny core devices. Static charges from a person or machinery can produce such damaging currents that are only partially blocked by the input-protection circuits in the periphery.
FIG. 1 shows a chip with several ESD-protection clamps. Core circuitry 250 contains core transistors 322, 324, which have a small channel length and can be damaged by currents at relatively low voltages. Core circuitry 250 receives a power supply voltage VDD, such as 1.8 volts, 1.2 volts, or some other value. There may be thousands of core transistors in core circuitry 250.
Protection from ESD pulses may be provided on each I/O pad, and by power clamp 326. Power clamp 326 is coupled between VDD and ground (VSS), and shunts current from an ESD pulse between the power rails.
Some cross-coupling may occur between different pads and core circuitry 250, such as through substrates and capacitances. An ESD pulse applied to one I/O pad 10 may be coupled into core circuitry 250 by this cross-coupling, causing damage to transistors 322, 324 in core circuitry 250. Power clamp 326 may shunt enough current from the ESD pulse to reduce such cross-coupling to prevent damage. ESD pulses applied to I/O pins may still couple into core circuitry 250, such as through power lines, but power clamp 326 may then be activated to reduce potential damage.
Power clamp 326 may also turn on for other ESD pulses such as those applied to I/O pins, when the ESD pulse is shunted through a diode in the I/O pin's ESD-protection structure to the internal VDD rail, causing an indirect VDD-to-VSS ESD pulse. For example, an ESD pulse applied to I/O pad 10 may cause ESD protection device 12 to turn on to conduct to VDD.
Each I/O pad 10 and 11 may be outfitted with one or more ESD protection devices 12, 16 and 14, 18 to protect against various possibilities. ESD protection device 16 turns on and discharges a negative ESD pulse from I/O pad 10 to ground. ESD protection device 18 turns on and discharges a negative ESD pulse from I/O pad 11 to ground. Likewise, ESD protection device 12 turns on and discharges a positive ESD pulse from I/O pad 10 to ground via the power clamp 326. ESD protection device 14 turns on and discharges a positive ESD pulse from I/O pad 11 to ground via the power clamp 326.
Some prior-art ESD protection structures have large-area capacitors, resistors, or transistors. Large size devices are expensive and undesirable. Some prior-art ESD-protection devices are not suited for standard CMOS processes, such as ESD-protection devices that use insulator layers in Silicon-On-Insulator (SOI) processes.
Diodes have been uses as ESD-protection structures, but the diode's I-V characteristics allow for high voltages when large ESD currents flow, and these high voltages can still damage core transistors. Some ESD-protection structures use two diodes in series rather than one diode, but such stacked diodes are undesirable in some environments due to the increased voltage drop of two diodes in series.
Silicon-Controlled Rectifiers (SCR's) have also been used successfully. Both an SCR and a diode may be used. However, simply having a diode and an SCR in an ESD-protection structure may produce erratic results that depend on the relative locations of the SCR and diode and other structures such as guard rings.
FIG. 2 shows a safe design window for an ESD protection device. I-V curve 94 shows the current flowing through a prior-art ESD structure as a function of the ESD pulse voltage.
Initially, at the start of an ESD event, the device is off. I-V curve 94 shows that the voltage rises from zero as a diode or other device turns on and conducts current until trigger voltage VTRIG. Above this trigger voltage, other devices in the ESD structure turn on, such as a MOS transistor or an SCR, allowing a larger current to flow. Just after trigger voltage VTRIG, as the current increases, the diode or SCR shunts the most current, and an avalanche current or similar mechanism may decrease the voltage, causing the snap-back of I-V curve 94. The lowest voltage during snap back is holding voltage VHOLD.
The holding voltage VHOLD should be greater than the power-supply voltage VDD to ensure that latch-up does not occur. Also, the maximum voltage, such as trigger voltage VTRIG, should be less than the device breakdown voltage VBD to ensure that permanent damage does not occur. Thermal failure can occur when breakdown voltage VBD is exceeded for too long of a period of time. IC reliability is enhanced when the ESD protection structure operates within the safe design window, so that I-V curve 94 operates between VDD and VBD.
Actual device curves may vary and show secondary effects not shown in simplified I-V curve 94. As IC processing technology improves and shrinks, VBD decreases due to thinner gate oxides and smaller device sizes in general. Also, VDD may be reduced. Thus the safe design window may shift and shrink. For a 5-volt power supply, the typical safe design window ranges from holding voltage VHOLD=5.5 volts to trigger voltage VTRIG=9 volts.
FIG. 3 shows a prior-art ESD-protection device using an N-well. A highly-doped P+ anode region 20 acts as the anode (A) and is formed in N-well 62. Isolation 34 can be created by growing field oxide or by other methods to isolate P+ anode region 20 from p-substrate 64 to prevent shorting of the ESD-protection device.
N+ cathode region 40 and P+ tap region 44 are formed on the surface of p-substrate 64. Both N+ cathode region 40 and P+ tap region 44 are connected to the cathode terminal. P+ tap region 44 biases p-substrate 64 with the cathode voltage, such as ground during normal operation.
A PNPN structure is formed that can act as an Silicon-Controlled Rectifier (SCR) during an ESD event. Once the SCR turns on, a large current can flow to shunt the ESD current. N-well 62 acts as the PNP base. The relatively low doping of N-well 62 can produce a low holding voltage, which can violate the safe design window. The relatively large size of N-well 62 produces a large boundary between N-well 62 and N-well 62. This large boundary can have a large capacitance, since capacitance is a function of the junction area. Such a large capacitance is undesirable since it slows down normal signaling.
Some applications such as Universal-Serial-Bus (USB) 3.0 specify a high transfer speed and are sensitive to capacitance on the ESD-protection devices. A Transient Voltage Suppressor (TVS) for ESD protection manufactured with a standard complementary metal-oxide-semiconductor (CMOS) process may have too much capacitance when large wells are incorporated into the TVS device.
What is desired is a Transient Voltage Suppressor (TVS) with a high holding voltage and low capacitance. An ESD-protection device with low capacitance that can be used for high-speed applications is desired. An SCR device constructed from diffusion diodes is desired for thermal stability and robustness.